1. Field of the Invention
The present invention relates generally to semiconductor integrated circuits of which high-speed operation is required, and more particularly, to semiconductor integrated circuits having a function of selecting one signal among a plurality of input signals, semiconductor integrated circuits having a full adding function and semiconductor integrated circuits comprising addition circuits having a carry look ahead function.
2. Description of the Related Art
A semiconductor integrated circuit includes a logic circuit for implementing a selection function, an addition function or a product function. In general, such a logic circuit employs a lot of transmission gates.
FIG. 1 is a diagram showing a construction of a conventional two-input selection circuit, which is disclosed in, for example, "Principle of CMOS VLSI.Design", published by Adison-Wesley Publishing Company, 1985, pp. 202.
In FIG. 1, the two-input selection circuit comprises a gate circuit TG1 for transmitting an input signal A received at an input node 1a to an output node 2 in response to selection signals SEL and SELB, and a gate circuit TG2 for transmitting an input signal B received at an input node 1b to output node 2 in response to control signals SEL and SELB.
Gate circuits TG1 and TG2 have the same construction and each comprises a p channel MOS transistor (p channel insulated gate type field effect transistor) Q1 and an n channel MOS transistor Q2. P channel MOS transistor Q1 of gate circuit TG1 has a gate receiving control signal SEL and p channel MOS transistor Q1 of gate circuit TG2 has a gate receiving control signal SELB.
N channel MOS transistor Q2 of gate circuit TG1 has a gate receiving complementary control signal SELB and n channel MOS transistor Q2 of gate circuit TG2 has a gate receiving control signal SEL.
Both of input signals A and B are binary logic signals assuming a logical value "1" or "0". In the following description, logic signals represented in binary form with logic "1" and "0" are simply referred to as logic signals.
Control signal SEL attains the logical value "1" or "0". Complementary control signal SELB is a negation signal of control signal SEL. More specifically, complementary control signal SELB attains the logical value "0" when control signal SEL attains the logical value "1" and attains the logical value "1" when control signal SEL attains the logical value "0".
Although the logic "1" and "0" can correspond to either of "H" and "L" potentials, it is assumed in the following description that logic "1" corresponds to an "H" potential and logic "0" to an "L" potential. Operation will be described in the following.
When control signal SEL is at "0", gate circuit TG1 is turned on (in a conductive state) and gate circuit TG2 is turned off (in a cut-off state). Logic signal A, out of logic signals A and B respectively input to input nodes 1a and 1b, is selected and transmitted to output node 2 through gate circuit TG1.
When control signal SEL is at "1", gate circuit TG1 is turned off, and gate circuit TG2 is turned on. In this case, logic signal B, out of input logic signals A and B, is transmitted to output node 2 through gate circuit TG2. In other words, the two-input selection circuit shown in FIG. 1 functions to select either of input logic signals A and B and output the selected logic signal as an output signal Z to output node 2.
FIG. 2 is a diagram showing a construction of a conventional full addition circuit, which is disclosed in, for example, Japanese Patent Publication No. 55-1619. In FIG. 2, the full addition circuit comprises an exclusive OR circuit 20a for receiving first and second logic signals A and B respectively applied to input nodes 1a and 1b to generate a control signal PG, an exclusive NOR circuit 20b for receiving first and second logic signals A and B to generate a complementary control signal PGB, an inverter circuit 13 for receiving a third logic signal C applied to an input node 1c and an inverter 14 for receiving logic signal A.
Exclusive OR circuit 20a generates a signal of "1" when logical values of logic signals A and B are different from each other. Exclusive NOR circuit 20b outputs a signal of "1" when the logical values of logic signals A and B are the same.
The full addition circuit further comprises a first gate circuit TG11 for selectively passing logic signal C to an output node 4a' in response to control signals PG and PGB, a second gate circuit TG12 for selectively transmitting an output signal CB from inverter circuit 13 to output node 4a' in response to control signals PG and PGB, a third gate circuit TG13 for selectively transmitting an output signal AB from inverter circuit 14 to an output node 4b' in response to control signals PG and PGB, and a fourth gate circuit TG14 for selectively transmitting output signal CB from inverter circuit 13 to output node 4b' in response to control signals PG and PGB.
Gate circuits TG11-TG14 have the same arrangement with each other, which is formed by a parallel connection of a p channel MOS transistor Q1 and an n channel MOS transistor Q2. Each gate of MOS transistors Q1 and Q2 receives control signal PG or PGB.
Gate circuit TG11 and gate circuit TG14 simultaneously become conductive and gate circuits TG12 and TG13 simultaneously become conductive. Gate circuits TG11, TG14 and gate circuits TG12, TG13 are turned on in a complementary manner.
A logic signal SB transmitted to output node 4a' is converted into an output logic signal S by an inverter circuit 15a. An output logic signal COB transmitted to output node 4b' is converted into an output logic signal CO by an inverter circuit 15b. Logic signals S and CO respectively transmitted to output nodes 4a and 4b are logic signals indicative of a first order digit and a second order digit of an addition result (A+B+C) of first to third logic signals A, B and C, respectively. Herein, a first order digit corresponds to a less significant bit and a second order digit corresponds to a more significant bit.
FIG. 3 is a table showing a relation between input logic signals and output logic signals of the full addition circuit shown in FIG. 2. FIG. 3 also shows control signals generated in this full addition circuit and operation states of the respective gate circuits. Operation will be briefly described in the following.
When input logic signals A and B attain the same logical value, control signal PG from exclusive OR circuit 20a goes to "0", while control signal PGB from exclusive NOR circuit 20b goes to "1". As a result, gate circuits TG12 and TG13 are turned on. Under this state, output logic signals CB and AB from inverter circuits 13 and 14 are transmitted to output nodes 4a' and 4b', respectively.
In other words, when logic signal A and logic signal B are equal in logical value to each other, a bit value S of a first order digit of an addition result on three input logic signals A, B and C is determined by a logic signal C. In this case, therefore, an output signal CB from inverter circuit 13 is selected as data for the first order digit and transmitted to output node 4a'.
For a more significant bit, when logic signal A is at "0", a second order digit of the addition result (A+B+C) provides a bit value of "0", and when logic signal A is at "1", the second order digit of the addition result (A+B+C) provides "1". In this case, therefore, output logic signal AB from inverter circuit 14 is transmitted to output node 4b'.
With logic signals A and B are different from each other, the addition result (A+B) is "1". In this case, a bit value of the first order digit of the sum of the three input logic signals (A+B+C) is equivalent to an inversion of third logic signals C. In this case, therefore, gate circuit TG11 is turned on in response to control signal PGB to select third logic signal C which is transmitted to output node 4a'.
In this case, the value of the second order digit of the addition result (A+B+C) is equal to a logical value of logic signal C. Therefore, output logic signal CB from inverter circuit 13 is selected by gate circuit TG14 and transmitted to output node 4b' in this case.
FIG. 4 is a diagram showing a construction of an n-bit full addition circuit for implementing a parallel addition of n bit binary numbers by using the full addition circuit shown in FIG. 2. In FIG. 4, the full addition circuit comprises n full adders F1-Fn. Each of the full adders F1-Fn has the same construction as that of the full addition circuit shown in FIG. 2.
Each of the full adders F1-Fn comprises logic signal input nodes 1a, 1b, and 1c and logic signal output nodes 4a and 4b. Full adder Fi (i=1-n) receives an i-th bit Ai of logic signal A at its input node 1a. Full adder Fi also receives an i-th bit Bi of logic signal B at its input node 1b and a carry output COi-1 from a full adder Fi-1 in the preceding or lower bit stage at its input node 1c. Full adder Fi outputs an i-th bit Si of the addition result S from its output node 4a and a carry output COi from its output node 4b. A carry input signal CI set to a fixed value (for example, logic "0") is applied to a carry input node 1c of full adder F1 in the first or the least significant bit stage.
Operation of the n-bit full addition circuit shown in FIG. 4 can be obtained by arranging the full addition circuits shown in FIG. 2 in an n-bit parallel fashion and connecting output bit COi of the second order digit with carry input IC of a full adder of a next more significant bit in a subsequent stage, a manner of which operation can be easily understood. In other words, the full addition circuit shown in FIG. 4 adds each bit at the same order of n-bit logic signals A and B. Carry generated at each bit is transmitted to a full adder of a next more significant bit to obtain an n-bit output signal S and a 1-bit carry output COn.
In FIG. 4, carry output COi is transmitted to a full adder of a next more significant bit, i+1, and operation time of the full addition circuit is determined by a propagation time period of such a carry output. In order to reduce the delay caused by this carry propagation, a full addition circuit having a carry look ahead function is often used.
FIG. 5 is a diagram showing a constitution of a conventional N-bit binary addition circuit having a carry look ahead function. In FIG. 5, N-bit binary addition circuit having a carry look ahead function comprises a plurality of stages each including at least three bits. In FIG. 5, each stage is shown in a block, and three blocks 31, 32 and 33 are illustrated as representatives. A single block may be provided in the full addition circuit. Carry look ahead circuit 41, 42 and 43 are provided corresponding to respective blocks 31-33. Each carry look ahead circuit receives a control signal from the corresponding block and a carry output from a full adder of the most significant bit in the corresponding block to determine whether carry should be caused in the block or not.
The output from a carry look ahead circuit is transmitted to a carry look ahead circuit in a higher order block as well as transmitted as a carry input to an addition block at a next higher order.
In the addition circuit shown in FIG. 5, the following operation is carried out. Where a carry input signal in a certain stage is transmitted through all full adders in the certain stage, the corresponding carry look ahead circuit outputs a carry signal to the subsequent stage before the carry signal is propagated throughout a transmission path including a chain of the full adders and then the carry out is output from the full adder of the most significant bit in the certain stage. As a result, a carry propagation delay is reduced.
FIG. 6 is a diagram showing a construction of second block 32 and carry look ahead circuit 42 shown in FIG. 5. Respective blocks and carry look ahead circuits in FIG. 5 have the same constructions as those shown in FIG. 6.
In FIG. 6, addition block 32 has the same construction as that of the full addition circuit shown in FIG. 4 and includes n full adders 50-1-50-n arranged in parallel for full addition of n-bits. A full adder 50-1 (i=1-n) comprises an input node 1a for receiving (m+i)th bit Am+i of logic signal A, an input node 1b for receiving (m+i)th bit Bm+i of logic signal B and an input node 1c for receiving a carry output COm+i-1 from a full adder of the next lower order bit. Full adder 51-i further includes an output node 4a for an addition Sm+i, an output node 4b for a carry COm+i and a control signal output node 4c for generating a control signal PG.
Control signals PGm+1-PGm+n respectively output from all the adders 50-1-50n are applied to a carry selection control signal generation circuit 30 included in carry look ahead circuit 42.
Carry selection control signal generation circuit 30 includes a logical product circuit for obtaining a logical product of control signals PGm+1-PGm+n. Carry selection control signal generation circuit 30 sets control signal SEL to logic "1" and control signal SELB to logic "0" when all the control signals PGm+1-PGn are at a logic "1" state. When at least one of control signals PGm+1-PGm+n is at a logic "0" state, carry selection control signal generation circuit 30 sets control signal SEL to logic "0". In other words, carry selection control signal generation circuit 30 sets control signal SEL to logic "1" when a carry signal is sequentially transmitted throughout all the full adders in addition block 32.
Carry look ahead circuit 42 further comprises gate circuits TG7 and TG8 for selectively passing either a carry signal COm+n of the most significant bit in addition block 32 or a carry input CI applied to full adder 50-1 of the least significant bit in response to control signals SEL and SELB from carry selection control signal generation circuit 30. Gate circuits TG7 and TG8 have the same arrangement comprising a parallel connection of a p channel MOS transistor Q1 and an n channel MOS transistor Q2. Each of gate circuits TG7 and TG8 is structured similarly to the selection circuit shown in FIG. 1.
When control signal SEL is at "1", gate circuit TG8 is turned on to transmit carry input CI as a carry signal CO to an output node 4. When control signal SEL is at "0", gate circuit TG7 is turned on to transmit carry output COm+n as carry signal CO to output node 4. Operation will now be described in the following.
Control signals PGm+1-PGm+n are carry propagation instructing signals each indicative of whether a carry is to be propagated or not in a corresponding adder. All the control signals PGm+1-PGm+n being at "1" indicate the carry input CI is transmitted throughout all the full adders 50-1-50-n. In this case, selection control signal SEL from carry selection control signal generation circuit 30 goes to "1" to transmit the carry signal CI as a carry out signal CO to a block in the subsequent stage through gate circuit TG8.
It is now assumed that one of the input logic signals in each of respective full adders 50-1-50-n is at "1" and the other at "0". In this case, all of PGm+1-PGm+n go to "1". (Control signal PGm+i is generated from EX-OR circuit 20a of FIG. 2). More specifically, in this state, when a carry signal CI at "1" is applied ahead circuit in the preceding stage, carry output COm+1 of full adder 1 (50-1) is first determined and is sequentially transmitted through all the full adders of more significant bits, resulting in generation of a corresponding carry signal COm+n from full adder 50-n of the most significant bit in this stage.
Such transmission of the carry signal CI through all the full adders 50-1-50-n is simultaneously determined by exclusive OR circuits included in full adders 50-1-50-n. Control signals (carry propagation instructing signals) PGm+1-PGm+n are output based on the respective determination results. Control signals PGm+n-PGm+1 are applied in parallel to carry selection control signal generation circuit 30.
Therefore, selection control signal SEL from carry selection control signal generation circuit 30 designates a carry propagation state to turn on gate circuit TG8 before carry signal CI is propagated through all the full adders 50-1-50-n. Carry signal CI input to full adder 50-1 of the least significant bit is transmitted to output node 4 as a carry input for a block in the subsequent stage through the on-state gate circuit TG8.
When both of the input logic signals in at least one of the full adders are at "1" or "0", a control signal PGm+j from the full adder reaches "0". In this state, gate circuit TG7 is turned on and gate circuit TG8 is turned off, whereby a carry signal COm+n from the full adder 50-n of the most significant bit is selected and output from output node 4 as a carry signal CO for a block in the subsequent stage.
As described in the foregoing, carry selection control signal generation circuit 30 makes a determination as to whether a carry signal should be propagated through all the full adders or not and enables transmission of the carry signal to a subsequent stage before output states of all the full adders 50-1-50-n are settled, thereby performing the addition of multi-bit logic signals at a high speed.
FIG. 7 shows constructions of first stage block 31 and corresponding carry look ahead circuit 41 in the N bit full addition circuit shown in FIG. 5. The circuit arrangement and operation thereof are the same as those of the circuit shown in FIG. 6 with the only difference being that a carry signal CI applied to the full adder 51-1 of the least significant bit is fixed to "0" of a ground potential level. Therefore, no detailed description will be given to the arrangement and operation of the circuit of FIG. 7.
In the first stage block shown in FIG. 7, the operation is only different from the operation of the circuit shown in FIG. 6 in that "0" state carry signal CO is transmitted to a block in the second stage when selection control signal SEL from carry selection control signal generation circuit 30 reaches "1".
A transmission gate constituted by a parallel connection of a p channel MOS transistor and an n channel MOS transistor generally has a characteristic that an input signal applied to an input node is transmitted to an output node without signal loss when it is ON and that the input node and the output node are reliably electrically cut off when it is OFF.
A change in an output of a certain circuit is equivalent to charging or discharging of load capacitance existing at the output of the circuit. It is therefore necessary to charge/discharge the output load capacitance at a high speed to rapidly cause the output change of the circuit.
In general, it is known that for speeding up an operation of a logic circuit formed using a MOS transistor, it is important to increase current drivability of the MOS transistor and reduce load capacitance of the same.
As shown in FIG. 8A, a MOS transistor comprises high concentration impurity regions 101 and 102 formed at the surface of a semiconductor substrate 100 and a conductive layer 103 formed on the surface of semiconductor substrate 100. Conductive layer 103 is referred to as a gate electrode and high concentration impurity regions 101 and 102 as source and drain regions. In an ordinary MOS transistor, which high concentration impurity region is used as a source region is determined according to the use of the transistor. In the following description, high concentration impurity region 101 connected to an output node is referred to as a drain region and high concentration impurity region 102 connected to an input node as a source region.
Gate electrode 103 is formed above a channel region between source and drain regions 101 and 102 with a gate insulation film 104 provided therebetween. Gate electrode 103 and drain region 101, and gate electrode 103 and source region 102 are electrically insulated by gate insulation film 104. Although not shown specifically, an interlayer insulation film for isolating different electrode interconnections is formed on the surface of semiconductor substrate 100.
With an MOS transistor structured as described above, a gate insulation film and an interlayer insulation film cause parasitic capacitance C1 to be generated between gate electrode 103 and drain region 101, while junction capacitance C2 is generated between drain region 101 and semiconductor substrate 100.
FIG. 8B is a top plan view of the MOS transistor shown in FIG. 8A. In FIG. 8B, a hatched region shows a channel region. Ordinarily, source region 102 and drain region 101 are formed in a self-alignment manner with respect to gate electrode 103. In the arrangement shown in FIG. 8B, a gate width W of gate electrode 103 determines the widths of drain region 101 and source region 102. The gate width is adjusted to determine the size of a transistor. An equivalent circuit of the MOS transistor is shown in FIG. 8C.
As shown in FIG. 8C, parasitic capacitances C1 and C2 exist in the drain region of the MOS transistor. For charging/discharging of an output node of the MOS transistor, it is therefore necessary to charge and discharge not only a signal line (a signal line to the output node) but also parasitic capacitances C1 and C2.
In a case of a transmission gate formed of a parallel connection of a p channel MOS transistor and an n channel MOS transistor, parasitic capacitance associated with the p channel MOS transistor and parasitic capacitance associated with the n channel MOS transistor existing at the output node should be charged and discharged. The structure of the p channel MOS transistor can be obtained by setting a conductivity type of each region to the opposite type in FIG. 8A showing the sectional structure of the n channel MOS transistor.
With the selection circuit structured as shown in FIG. 1, gate circuits TG1 and TG2 has large parasitic capacitances at the respective portions connected to output node 2. When gate circuit TG1 is turned on, for example, input logic signal A transmitted through gate circuit TG1 should charge/discharge not only output node 2 but also the parasitic capacitance existing at the output portion of gate circuit TG2. It is therefore impossible to settle a signal potential of output node 2 at a high speed, resulting in an increased delay in signal propagation.
In particular, when either of input logic signals A and B should be constantly output at a higher speed (in a case of a carry signal, for example), when a logical value of either of the logic signals is fixed and when it is not particularly necessary to transmit either of the logic signals at a high speed, load capacitance at the output node of a non-selected gate circuit causes an increased delay in signal propagation.
A conventional full addition circuit has the construction as shown in FIGS. 2 and 4. In the full addition circuit as shown in FIG. 2, gate circuits TG11-TG14 are provided at the output node and large load capacitance exist at an output of each of the gate circuits TG11-TG14.
In general, in parallel addition of multi-bit binary numbers A and B, Ai and Bi of each respective order are simultaneously applied to a full adder which in turn receives a carry from a next lower order bit, which carry is added to the addition result of the bits Ai and Bi. The carry signal from a full adder is transmitted to a full adder in the subsequent stage. Therefore, in the parallel addition of multi-bit binary numbers, bits at the respective orders are simultaneously applied to corresponding full adders in parallel, while a carry signal is serially transferred through the full adders.
Therefore, addition in a more significant bit should be suspended until addition in a less significant bit is finished. The path for propagating the carry signal from the least significant bit to the most significant bit is the longest propagation path requiring the greatest propagation time period. The maximum propagation time period determines an operation time period of the full addition circuit.
It is therefore necessary to reduce a propagation time of this carry signal to the minimum. In the arrangement shown in FIG. 2, a carry signal C transmitted from a preceding stage to input node 1C is transmitted to output node 4b' through inverter circuit 13 and gate circuit TG14. A carry signal COB at the output node 4b' is transmitted to carry signal input node 1c of a full adder in the subsequent stage through inverter circuit 15b. There exists another path for transmitting a signal to output node 4b'. This path is used for transmitting logic signal A applied to input node 1a through inverter circuit 14 and gate circuit TG13.
In the arrangement of FIG. 2, reduction of an operation time of the full addition circuit requires a delay time at a path for transmitting the carry signal C to be smaller than that of a path for transmitting the logic signal A.
However, in a case in which gate circuit TG14 is turned on to transmit the carry signal C from the preceding stage to output node 4b', load capacitance existing at the output portion of the off-state gate circuit TG13 causes delay in transmission of the input carry signal C.
In addition, there exists a path for propagating a carry signal other than the above-described shortest carry signal propagation path. That is a transmission path from an adder to an adder at a subsequent stage. In general, the higher is the order of a bit at which a chain for a carry signal (a path for serially transmitting the carry signal) starts, the shorter is the time which the carry signal requires for its propagation through the chain. As long as a time required for the propagation of the carry signal through the chain is equal to or shorter than the time period required for the propagation through the longest carry signal propagating path (a path for the propagation through all the full adders), performance in operating speed of the addition circuit as a whole is not deteriorated even if a time required for propagating the carry signal through the chain is increased.
However, with a transistor size of gate circuit TG13 being equal in all the full adders, parasitic capacitance existing at an output node in each full adder becomes equal. Therefore, in this case, the same delay time is accumulated in each full adder, so that parasitic capacitance existing at output node 4b' of gate circuit TG13 causes an increase in a delay time of a carry signal received from a next less significant bit and transmitted through gate circuit TG14.
In general, for parallel addition of multi-bit binary numbers as shown in FIG. 4, a carry signal CI is fixed to for example, "0", in a full adder F1 for the addition of the least significant bits. In the arrangement shown in FIG. 2, with a logical value of a carry signal fixed as described above, a delay time in transmitting the carry signal CI to output node 4b' becomes less than that in transmitting input logic signal A to output node 4b'.
In FIG. 2, when a logical value of logic signal C is fixed, a potential level from the node 1c as far to the input portion of gate circuit TG14 is fixed. On the other hand, logic signal A has a logical value varying according to an input augend. Time required for propagation of this logic signal A to output node 4b' becomes longer than time required for propagation of this logic signal C to output node 4b' by a time required for propagation of this logic signal A from input node 1a to gate circuit TG13.
In a case in which gate circuit TG13 is turned on to transmit logic signal AB, applied from inverter circuit 14, to output node 4b', parasitic capacitance existing at the output portion of the off state gate circuit TG14 causes delay in propagation of logic signal AB. In this case, when input logic signal A is transmitted as a carry signal to a full adder in a subsequent stage, the propagation time is increased to prevent high-speed transmission of the carry signal.
In addition, the N bit binary addition circuit having a carry look ahead function has the arrangement shown in FIGS. 5 and 6. In this arrangement of the N bit binary addition circuit, a path on which a carry signal from a preceding stage is repeatedly selected by a carry look ahead circuit to become a carry signal for a subsequent stage requires the greatest propagation time for propagating a carry signal. The carry look ahead circuit comprises gate circuit TG8 for passing a carry signal from a carry look ahead circuit in a preceding stage and gate circuit TG7 for passing a carry signal (COm+n in FIG. 6) from the corresponding addition block 32.
Therefore, when the carry look ahead circuit passes a carry signal from a carry look ahead circuit in the preceding stage, parasitic capacitance existing at the output of gate circuit TG7 causes a delay in carry signal propagation.
When the carry signal propagation path includes a path for selectively transmitting a carry signal from the corresponding addition block to a carry look ahead circuit in a subsequent stage, that is, when a carry signal output from an intermediate block is transmitted through a chain of carry look ahead circuits, the higher the order of a stage is at which the chain starts, the shorter a time period becomes which is required for propagation of the carry signal through the chain.
As long as a time required for propagation of a carry signal through a chain of carry look ahead circuits is equal to or less than a propagation time (the longest propagation time) required for the carry signal to pass through all the carry look ahead circuits, performance in speed of the full addition circuit is not deteriorated. Therefore, higher order stage can use a longer time to pass through gate circuit TG7 in a carry look ahead circuit. Every carry look ahead circuit includes transistors of the same size for the gate circuit TG7, and parasitic capacitance of the same value is produced at the output portion of each gate circuit TG7 in each respective carry look ahead circuit. When gate circuit TG8 selects and transmits a carry signal from a carry look ahead circuit in a preceding stage, delay time caused by the parasitic capacitance at the output of the gate circuit TG7 is accumulated. Such parasitic capacitance therefore accumulatively increases the time which is required for propagation of a carry signal through carry look ahead circuits.
Now a case is considered that a logical value of a carry signal applied to a full adder of the least significant bit is fixed or predetermined as shown in FIG. 7. The following case allows a path to make propagation time of a carry signal generated from a preceding stage the longest. That is, it is the case where addition of first and second input signals A1 and B1 generates a carry in full adder 51-1 of the least significant bit in the first stage and in all of more significant bits other than the least significant bit, a carry signal from a full adder of a next lower significant bit determines an output state of a carry signal. In other words, it is the case where a carry signal from carry look ahead circuit 41 in the first stage is provided by a carry signal COm from full adder 51-n of the most significant bit in the corresponding addition block 31 in the first stage.
In the N bit binary addition circuit, propagation time becomes the longest when a carry signal sequentially passes through carry look ahead circuits in the respective stages, starting from a carry look ahead circuit in the first stage. High-speed propagation of this carry signal enables high-speed operation of the N bit binary addition circuit.
However, load capacitance existing at the output of gate circuit TG8 prevents gate circuit TG7 from transmitting carry signal COm from the most significant bit to a carry look ahead circuit in a subsequent stage at a high speed, resulting in an increase in a propagation time of a carry signal.